1. Field of Use
The present invention relates to apparatus for shifting information and more particularly to shifting apparatus which can be efficiently implemented in gate array form.
2. Prior Art
To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard off-the-shelf circuits, custom circuits and gate arrays. The gate array involves the use of a standard array of a large number of gate circuits diffused into a chip. The metalization pattern converting these gate circuits into functional custom circuits is processed according to the customer's requirements.
A macrocell array is an extension of the gate array concept. A macrocell is an array subsection performing a higher level logic function than a basic gate. A macrocell array is an array circuit in which macro functions used to define logic simulations are directly implemented within the basic cell structure rather than formed by interconnecting gates. Each cell in a macrocell array contains a number of unconnected transistors and resistors. A metalization process transforms the interconnected transistors and resistors within each cell into Small Scale Integrated (SSI) logic functions called macros. The macros take the form of standard logic elements such as dual type "D" flip-flops, multiplexers and many other functions.
The high density packing of a macrocell array chip offers substantial reductions in system component count and power dissipation. Thus, it becomes desirable to utilize such chips in computer designs.
With recent advances, it is possible for a processor to execute millions of instructions per second (MIPS). Many different types of such instructions simply involve the transfer or manipulation of operands through high speed adder circuits.
This can be easily accomplished within a system or machine cycle of operation. However, it is much more difficult and time-consuming to perform shifting types of operations within the same time period particularly where large operands are involved. This has been found to be particularly true where shifting networks have utilized shift registers and multiplexers. In shift register implementations, the time required to execute a multibit shift is normally dependent upon the number of shifts required. Multiplexer implementations using single bit or several bits at a time shifts require several passes or cycles in order to provide larger operand shifts, in addition to requiring a considerable number of interconnections.
The interconnection problem is compounded when a large number of bits are required to be shifted at a time. For example, it was found that when it was attempted to simply expand a prior art multiplexer arrangement capable of shifting right or left by eight bits for a total shift of 16 to accommodate a larger number of shifts, it was found to be too slow and require a considerable amount of chip area when implemented in macrocell array form.
Accordingly, it is a primary object of the present invention to provide a shifter in which multibit shifts can be achieved within a single cycle of operation.
It is a further object of the present invention to provide a shifter which has a minimum number of interconnections and multiplexer circuits so as to be readily implementable in macrocell array form.